Combinational Full Adder¶
Verilog Code¶
RST Directive¶
1.. no-license:: ../code/verilog/adder.v
2 :language: verilog
3 :linenos:
Result¶
19module ADDER (
20 a, b, cin,
21 sum, cout
22);
23 input wire a;
24 input wire b;
25 input wire cin;
26
27 output wire sum;
28 output wire cout;
29
30 // Full adder combinational logic
31 assign sum = a ^ b ^ cin;
32 assign cout = ((a ^ b) & cin) | (a & b);
33endmodule
Yosys BlackBox Diagram¶
RST Directive¶
1.. hdl-diagram:: ../code/verilog/adder.v
2 :type: yosys-bb
3 :module: ADDER
Result¶
Yosys AIG Diagram¶
RST Directive¶
1.. hdl-diagram:: ../code/verilog/adder.v
2 :type: yosys-aig
3 :module: ADDER
Result¶
NetlistSVG Diagram¶
RST Directive¶
1.. hdl-diagram:: ../code/verilog/adder.v
2 :type: netlistsvg
3 :module: ADDER
Result¶
