Sphinx HDL Diagrams
Sphinx HDL Diagrams

Combinational Full Adder

Verilog Code

RST Directive

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.. no-license:: ../code/verilog/adder.v
   :language: verilog
   :linenos:

Result

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module ADDER (
	a, b, cin,
	sum, cout
);
	input wire a;
	input wire b;
	input wire cin;

	output wire sum;
	output wire cout;

	// Full adder combinational logic
	assign sum = a ^ b ^ cin;
	assign cout = ((a ^ b) & cin) | (a & b);
endmodule

Yosys BlackBox Diagram

RST Directive

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.. hdl-diagram:: ../code/verilog/adder.v
   :type: yosys-bb
   :module: ADDER

Result

/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/latest/docs/code/verilog/adder.v

Yosys AIG Diagram

RST Directive

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.. hdl-diagram:: ../code/verilog/adder.v
   :type: yosys-aig
   :module: ADDER

Result

/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/latest/docs/code/verilog/adder.v

NetlistSVG Diagram

RST Directive

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.. hdl-diagram:: ../code/verilog/adder.v
   :type: netlistsvg
   :module: ADDER

Result

/home/docs/checkouts/readthedocs.org/user_builds/sphinxcontrib-hdl-diagrams/checkouts/latest/docs/code/verilog/adder.v