CARRY4 example for Series 7 FPGA¶
CARRY4 defined directly¶
19module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
20 assign O = S ^ {CO[2:0], CI | CYINIT};
21 assign CO[0] = S[0] ? CI | CYINIT : DI[0];
22 assign CO[1] = S[1] ? CO[0] : DI[1];
23 assign CO[2] = S[2] ? CO[1] : DI[2];
24 assign CO[3] = S[3] ? CO[2] : DI[3];
25endmodule
1.. hdl-diagram:: ../code/verilog/carry4-whole.v
2 :type: netlistsvg
3 :module: CARRY4
CARRY4 defined by components¶
19`include "muxcy.v"
20`include "xorcy.v"
21
22module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
23 wire CIN = CI | CYINIT;
24
25 MUXCY muxcy0 (.O(CO[0]), .CI(CIN), .DI(DI[0]), .S(S[0]));
26 MUXCY muxcy1 (.O(CO[1]), .CI(CO[0]), .DI(DI[1]), .S(S[1]));
27 MUXCY muxcy2 (.O(CO[2]), .CI(CO[1]), .DI(DI[2]), .S(S[2]));
28 MUXCY muxcy3 (.O(CO[3]), .CI(CO[2]), .DI(DI[3]), .S(S[3]));
29
30 XORCY xorcy0 (.O(O[0]), .CI(CIN), .LI(S[0]));
31 XORCY xorcy1 (.O(O[1]), .CI(CO[0]), .LI(S[1]));
32 XORCY xorcy2 (.O(O[2]), .CI(CO[1]), .LI(S[2]));
33 XORCY xorcy3 (.O(O[3]), .CI(CO[2]), .LI(S[3]));
34endmodule
19module MUXCY(output O, input CI, DI, S);
20 assign O = S ? CI : DI;
21endmodule
19module XORCY(output O, input CI, LI);
20 assign O = CI ^ LI;
21endmodule
MUXCY¶
1.. hdl-diagram:: ../code/verilog/muxcy.v
2 :type: netlistsvg
3 :caption: muxcy.v
4 :module: MUXCY
muxcy.v¶
XORCY¶
1.. hdl-diagram:: ../code/verilog/xorcy.v
2 :type: netlistsvg
3 :caption: xorcy.v
4 :module: XORCY
xorcy.v¶
CARRY4 without flatten¶
1.. hdl-diagram:: ../code/verilog/carry4-bits.v
2 :type: netlistsvg
3 :module: CARRY4
4 :caption: carry4-bits.v without flatten
carry4-bits.v without flatten¶
CARRY4 with flatten¶
1.. hdl-diagram:: ../code/verilog/carry4-bits.v
2 :type: netlistsvg
3 :module: CARRY4
4 :flatten:
5 :caption: carry4-bits.v with flatten
carry4-bits.v with flatten¶